It is hard to find a new Pentium 4 socket 478
top of that, if you need DMA support, your task has become even more difficult.
There are a few here and there. We found one and are listing it here.
If you are wondering what DMA is, the following text will help.
A DMA controller can generate addresses and initiate memory read or write
cycles. It contains several registers that can be written and read by the CPU.
These include a memory address register, a byte count register, and one or more
control registers. The control registers specify the I/O port to use, the
direction of the transfer (reading from the I/O device or writing to the I/O
device), the transfer unit (byte at a time or word at a time), and the number of
bytes to transfer in one burst.
To carry out an input, output or memory-to-memory operation, the host processor
initializes the DMA controller with a count of the number of words to transfer,
and the memory address to use. The CPU then sends commands to a peripheral
device to initiate transfer of data. The DMA controller then provides addresses
and read/write control lines to the system memory. Each time a word of data is
ready to be transferred between the peripheral device and memory, the DMA
controller increments its internal address register until the full block of data
DMA transfers can either occur one word at a time, allowing the CPU to access
memory on alternate bus cycles-this is called cycle stealing since the DMA
controller and CPU contend for memory access. In burst mode DMA, the CPU can be
put on hold while the DMA transfer occurs and a full block of possibly hundreds
or thousands of words can be moved. Where memory cycles are much faster than
processor cycles, an interleaved DMA cycle is possible, where the DMA controller
uses memory while the CPU cannot.
In a bus mastering system, both the CPU and peripherals can be granted
control of the memory bus. Where a peripheral can become bus master, it can
directly write to system memory without involvement of the CPU, providing memory
address and control signals as required. Some measure must be provided to put
the processor into a hold condition so that bus contention does not occur.